A current mirror circuit is a circuit that mirrors, or copies, the current flowing in one active device of the circuit in another active device of the circuit while keeping the output current of the circuit constant regardless of the output load. A wide variety of current mirror circuits exist. FIG. 1 illustrates a block diagram of basic bipolar junction transistor (BJT) current mirror circuit. Ideally, the output current Iout is equal to the input current Iref times the ratio of Q2/Q1. However, the base currents of BJTs Q1 and Q2 are also drawn from Iref, which reduces the effective Iref. As a result, the output current Iout is smaller than expected. When BJT Q2 is large, or there are a greater number of output transistors connected in parallel, the error of Iout is significantly large.
FIG. 2 illustrates a block diagram of a BJT current mirror circuit that employs a third BJT Q3 to perform base current compensation. With the exception that the base current of BJT Q3 is drawn from the input current Iref, all base currents come from the emitter of BJT Q3 so that the Iout error is almost negligible. The feedback loop stability is compensated by capacitor Cf. However, the minimum power supply voltage, VDD, has to be greater than two times of the bipolar base-emitter voltage plus the saturation voltage of the current source Iref. In general, the power supply voltage VDD should be greater than ˜2.2 V. Therefore, this circuit generally is not suitable for low voltage (i.e., less than about 1.8 volt (V) operation.
FIG. 3 illustrates a block diagram of a current mirror circuit that employs an N metal oxide semiconductor field effect transistor (NMOS) to perform base current compensation. The BJT Q3 shown in FIG. 2 is replaced by NMOS M3 in FIG. 3. The NMOS transistor does not draw any current from input current Iref, and therefore there is no Iout error caused by base currents. As in the circuit of FIG. 2, the feedback loop stability in the circuit of FIG. 3 is compensated by capacitor Cf. All base currents are provided by NMOS M3. The minimum power supply voltage VDD needs to be greater than the bipolar base-emitter voltage plus the gate-source voltage of NMOS M3 plus the saturation voltage of the current source Iref. The result is similar to the above one in that this circuit is also not suitable for low voltage (i.e., less than about 1.8 V) operation.
Accordingly, a need exists for a current mirror circuit that is capable of low-voltage operation.